Intel has announced new chip technologies that promise to make it a more formidable future competitor of Taiwan’s TSMC and South Korea’s Samsung Electronics and that put the 7nm processor built by China’s SMIC for Huawei’s new 5G smartphone in a new perspective.
In a keynote address at the Intel Innovation 2023 event that opened in San Jose on September 19, CEO Pat Gelsinger said the company’s 2nm process (20A, or 20 angstroms, which equals 2 nanometers) will be production-ready in the first half of 2024 and its 18A process in the second half of the same year.
Intel’s 18A silicon should go into the fab in the first quarter of next year, leading to high-volume production in 2025.
If all goes according to plan, it would mark the success of Intel’s “5 Nodes in 4 Years” catch-up strategy announced by Gelsinger in 2021. TSMC and Samsung Electronics have 3nm processes in production now and plan to launch 2nm in 2025.
Intel’s “Beyond 5 Nodes in 4 Years” Roadmap:
Intel 7: Now in high-volume manufacturing
Intel 4: Now ramping up production
Intel 3: 2H 2023 – manufacturing ready, sampling
Intel 20A: 1H 2024 – on track for manufacturing
Intel 18A – 2H 2024 – on track for manufacturing
Intel has its own process roadmap terminology, which can be confusing. The XDA Developers tech news portal explains:
“For reference, Intel 7 is what the company names its 10nm process, and Intel 4 is what it names its 7nm process. Where the names come from (even though one could argue that they’re misleading) is that Intel 7 has a very similar transistor density to TSMC’s 7nm, despite Intel 7 being built on a 10nm process. The same goes for Intel 4… [which is] the first of Intel’s fabrication processes to make use of extreme ultraviolet [EUV] lithography… With that said, where things become very interesting is with 20A and 18A. 20A (the company’s 2nm process) is said to be where Intel will reach “process parity.”
Tom’s Hardware fills in the gap with this comment: “Intel 3 (previously known as 5nm)… uses extreme ultraviolet [EUV] lithography and is generally a refined Intel 4 production node (previously known as 7nm). Compared to Intel 4, Intel 3 promises an 18% higher performance per watt efficiency, denser high-performance library, reduced via resistance, and increased intrinsic drive current.”
Intel 3 process technology will be used in the volume production of the new data center and server processors at Granite Rapids and Sierra Forest scheduled for next year.
In comparison, the 7nm Kirin 9000 processor used in Huawei’s Mate 60 Pro smartphone was fabricated by SMIC, China’s leading foundry, using a 7nm process with DUV (deep ultraviolet) ArF immersion lithography.
The export of more advanced EUV lithography to China is banned under US sanctions, so this was the only solution available for the company.
US government officials and other commentators were surprised that this could be done, but industry specialists were not. With time, SMIC will probably be able to implement a 5nm process using the same equipment but that will be the limit.
On September 20, Intel announced the first use of EUV lithography systems in high-volume manufacturing in Europe at its new fab in Ireland. The machines will support Intel 4 starting this year and Intel 3 starting in 2024.
ASML’s next-generation High Numerical Aperture (High-NA) EUV systems will be used at the 18A process node. At Intel Innovation 2023, Gelsinger said the first of these machines will arrive at the company’s facility in Oregon in time for Christmas.
According to ASML, “That machine, the 0.55 numerical aperture (NA) Twinscan EXE:5000 pilot scanner, is being developed for chipmakers so that they may learn how to efficiently use High-NA EUV technology. Following those R&D efforts, high volume manufacturing of chips using High-NA scanners expected to commence in 2025, when ASML begins shipping the commercial-grade Twinscan EXE:5200 scanner.”
Compared with the 0.33 NA optics in current EUV systems, High-NA will greatly reduce the resolution limit, enabling “geometric chip scaling well into the next decade.” A critical technology for enabling nodes below 2nm/20A, it raises the bar for China’s lithography equipment developers.
Moreover, Intel announced on September 18 the successful development of its first glass substrates for the next-generation advanced packaging it plans to introduce in the second half of the decade. Intel explains the significance of this development as such:
“As the demand for more powerful computing increases and the semiconductor industry moves into the heterogeneous era that uses multiple ‘chiplets’ in a package, improvements in signaling speed, power delivery, design rules and stability of package substrates will be essential. Glass substrates possess superior mechanical, physical and optical properties that allow for more transistors to be connected in a package, providing better scaling and enabling assembly of larger chiplet complexes (called ‘system-in-package’) compared to organic substrates in use today. Chip architects will have the ability to pack more tiles – also called chiplets – in a smaller footprint on one package, while achieving performance and density gains with greater flexibility and lower overall cost and power usage.”
Compared with the organic packaging materials (epoxy resin, etc.) used today, “glass offers distinctive properties such as ultra-low flatness and better thermal and mechanical stability, resulting in much higher interconnect density in a substrate.”
“By the end of the decade, the semiconductor industry will likely reach its limits on being able to scale transistors on a silicon package using organic materials, which use more power and include limitations like shrinkage and warping. Scaling is crucial to the progress and evolution of the semiconductor industry, and glass substrates are a viable and essential next step for the next generation of semiconductors.”
They will be used first in data center, AI and graphics applications.
Meanwhile, Intel is working with the Universal Chiplet Interconnect Express (UCle), a diverse international consortium of which it was one of the founding members in March 2022.
The idea behind the UCle specification is to provide an open standard ubiquitous package level interconnect allowing system-on-chip (SoC) designers to combine chiplets from different suppliers, addressing “customer requests for more customizable package-level integration, connecting best-in-class die-to-die interconnect and protocols from an interoperable, multi-vendor ecosystem.”
The Merriam-Webster dictionary definition of “chiplet” is “a small modular integrated circuit component that is designed to provide a specific function.”
UCle now has more than 120 members, including founding board members AMD, Arm, ASE, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung and TSMC, additional board members Alibaba and Nvidia, and dozens of contributor members including Advantest, Applied Materials, Beijing Stream Computing, Bosch, Cadence, Ericsson, Global Foundries, IBM, imec, Keysight, Juniper Networks, Mercedes-Benz, Micron, MediaTek, Shanghai UniVista, Siemens, SK Hynix, Synopsis, Teradyne, Tongfu Microelectronics, Xi’an UniIC Semiconductors, UNISOC, VeriSilicon and Xspeedic.
The presence of IC designers and manufacturers, electronic design automation suppliers, semiconductor production and test equipment makers, a leading research institution, cloud service and software providers, telecom equipment makers and other manufacturing companies from around the world – including several Chinese companies – demonstrates the collaborative direction of what Intel calls the “Siliconomy.”
It is directly opposite to the fragmenting, supply chain-cutting, subsidizing and nationalistic bent of US politicians.
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